CPU
Super Computers
1943 Colussus
1945 ENIAC Electronic Numerical Integrator And Computer
1948 Manchester Baby / Manchester Mark 1 / 1951 Ferranti Mark 1
1949 EDSAC
1949 EDVAC, BINAC, ORDVAC
1951 TRADIC Bell Labs Transistors
1951 UNIVAC, UNISYS, ILLIAC, SILLIAC
1953 Remington Rand UNIVAC 1103, ERA 1103 (by Seymour Cray)
1954 IBM 650
CTC Computer Terminal Corporation
1969 CTC Datapoint 3300
CDC
CRAY
IBM System/360
DEC PDP-1
| 1955 | Shockley Semiconductor Laboratory (Caltech / MIT / Bell labs) | ||
| 1957 | Fairchild Semiconductor (traitorous eight) | ||
| 1968 | Intel (Noyce and Moore) | ||
| 1974 | Zilog (Federico Faggin and Masatoshi Shima) |
Intel 4004, 8008, 8088, 8080 Zilog Z80 is a 5V only spinoff from an Intel 8080, dropping the need for 12V
Zilog Z80 is a 5V only spinoff from an Intel 8080, dropping the need for 12V
Zilog (Exxon) ... > IXYS > Littlefuse
https://floooh.github.io/visualz80remix/
Motorola 6800, 68000, 68020
MOS 6502, 6510
Acorn ARM
TI, Sun, Dec, IBM
https://archive.computerhistory.org/resources/text/Oral_History/Zilog_Z80/102658073.05.01.pdf
Micro Controller
Intel MCS-48 8048
Intel MCS-51 8051
RISC Berkley / IBM MIPS Stanford IBM PowerPC SUN Sparc DEC Alpha
Feature set / Instructions
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, EM64T, VT-x, AES, AVX, AVX2, FMA3, TSX
Moore's Law / Transistors
| Integration level | Year | Logic gates | ||
|---|---|---|---|---|
| SSI | Small Scale Integration | 1964 | ||
| MSI | Medium Scale Integration | 1968 | 20-200 | |
| LSI | Large‐scale integration | 1970 | 200-2000 | 10 µm |
| VLSI | Very large‐scale integration | 1980 | 2.000-20.000 | 1.5 µm |
| ULSI | Ultra large‐scale Integration | 1990 | 20.000-200.000 | 600 nm |
| SLSI | Super large‐scale integration | 2000 | 200.000- 2 million | 130 nm |
| 2010 | 2 million - 20 million | 22 nm | ||
| 2020 | 20 million - 200 million | 5 nm |
CISC v.s. RISC
RISC is a philosophy to use simpler instructions to achieve the same as complex instruction. For example for AES rowshifting an Intel can use XMM instructions to shift multiple rows in one operation, while RISC processors need to loop through the bytes and execute simpler instructions. It takes longer to execute, but without SIMD the processor is smaller, cheaper and wins in power efficiency.
Intel CISC
PCLMULHQHQDQ xmmreg,xmmrm
ARM RISC
result = operand1 EOR operand2;
for s = 0 to segments-1
Elem[result, s, 128] = AESSubBytes(AESShiftRows(Elem[result, s, 128]));
RISC
| DARPA VLSI Project University funding | ||
| 1980 | University of Berkley (David Patterson) | |
| 1981 | RISC I | 44,500 transistors, 31 instructions, 78 32-bit registers
research project |
| RISC Foundation | Open ISA free to implement | |
| 2015 | RISC V | |
MIPS
https://www.cpushack.com/2013/09/28/realtek-rtl8186-mips-by-lexra/
http://jonahprobell.com/lexra.html
| 1976 | IBM 801 | first conceptual RISC processor |
| 1980 | DARPA VLSI Project University funding | |
| MIPS | Stanford University (John Hennessy) | |
| 1984 | MIPS Computer Systems, Inc. | |
| 1992 | Acquired by SGI | |
| 1998 | SGI spun off MIPS | |
| 2008 | lost money on buying and selling Chipidea | |
| 2013 | bought by Imagination Technologies (PowerVR) | |
| 2022 | Adopted RISC-V |
| 1997 | Lexra based on MIPS-I instruction set (Not the core license) | |
| 1998 | Patent on "unaligned loads and stores" | |
| 2003 | Lexra bankrupt | |
| 2006 | RTL8196E | Realtek continues to use Lexra Cores (RLX4181) |
ARM
Cortex-A Microprocessors, with an MMU, for Rich OS e.g. BSD/Linux/Windows)
Cortex-R Realtime processors
Cortex-M Microcontrollers for RTOS Task Scheduling
ARMv7-M ISA
M0+ von neuman (instruction and data share the same bus)
M3
M4
M7
ARMv8-M
M23 Trustzone
M33
M35P
Armv8.1-MM55
M85
Segger
SEGGER J-Link EDU Mini - JTAG/SWD Debugger
https://thepihut.com/products/segger-j-link-edu-mini-jtag-swd-debugger