ESP32

MICROCONTROLLERS

QSPI

doit esp32 dev kit v1
921600
80Mhz

Espressif

https://www.espressif.com/en/products/modules

https://www.esp32.com/viewforum.php?f=23

ESP8266	LX6 single core
ESP32	LX6 single/dual core
S2, S3	LX7
H2	RISC-V
C2, C3, C6	RISC-V

ESP8266

https://github.com/SmartArduino/SZDOITWiKi/wiki/ESP8266---ESP32

ESP32

DOIT Esp32 DevKit v1
ESP-WROOM32
Xtensa LX6

Arduino

Platform.io

921600 80Mhz

https://docs.platformio.org/en/latest/boards/espressif32/esp32doit-devkit-v1.html

RTOS

FreeRTOS

https://github.com/FreeRTOS/FreeRTOS-Kernel

Thread

https://www.espressif.com/en/news/ESP32_H2

ESP32-H2
Risc V
Thread, Zigbee, Bluetooth LE

ESP32-S3

https://openthread.io/guides/border-router/espressif-esp32

https://github.com/espressif/qemu

https://github.com/Ebiroll/qemu_esp32

ULP ESP32 Ultra Low Power Co-Processor

QSPI

QSPI

Python39\Scripts\esptool.exe read_flash --spi-connection HSPI 0 0x400000 flash_dump.bin

esptool.py v3.0
Found 1 serial ports
Serial port COM3
Connecting....
Detecting chip type... ESP32
Chip is ESP32-D0WDQ6 (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
Crystal is 40MHz
MAC: 24:6f:28:24:22:2c
Uploading stub...
Running stub...
Stub running...
Configuring SPI flash mode...
4194304 (100 %)
4194304 (100 %)
Read 4194304 bytes at 0x0 in 379.9 seconds (88.3 kbit/s)...
Hard resetting via RTS pin...

https://github.com/espressif/esp-idf/tree/master/components/spi_flash

https://my-esp-idf.readthedocs.io/en/latest/api-reference/peripherals/spi_master.html https://github.com/espressif/arduino-esp32/blob/master/tools/sdk/include/esp32/rom/spi_flash.h ESP32 chip have 4 SPI slave/master SPI0, SPI1, HSPI and VSPI. SPI0 is used as an SPI master to access Flash and ext-SRAM SPI1 is connected to the same hardware lines as SPI0 HSPI and VSPI all have three chip select lines

use 40M clock SPI Flash can use 2 lines or 4 lines mode. If you use 2 lines mode, you can save two pad SPIHD and SPIWP for gpio. Common SPI command to configure Flash to QIO mode

miso - Also known as q, this is the input of the serial stream into the ESP32 mosi - Also known as d, this is the output of the serial stream from the ESP32 sclk - Clock signal. Each data bit is clocked out or in on the positive or negative edge of this signal quadwp - Write Protect signal. Only used for 4-bit (qio/qout) transactions. quadhd - Hold signal. Only used for 4-bit (qio/qout) transactions.

In master mode SPID = MOSI = data out SPIQ = MISO = data in

https://drive.google.com/file/d/11-IH-38VJOXbFJ1ybB1i2Cvcl9n3pSTU/view

SPI.begin SPI.setBitOrder SPI.setClockDivider SPI.setDataMode SPI.transfer

spi_bus_initialize

https://github.com/espressif/esptool/wiki/SPI-Flash-Modes

https://github.com/espressif/esptool#read-spi-flash-id

Particle Xenon

https://docs.particle.io/xenon/

\.platformio\packages\framework-espidf\components\esptool_py

https://docs.platformio.org/en/latest/frameworks/zephyr.html#framework-zephyr

Micro:bit

qemu-system-arm -M microbit -device loader,file=test.hex

https://www.qemu.org/docs/master/system/arm/imx25-pdk.html

Bootrom –> SPL –> BL31 –> BL33(u-boot) –> Linux kernel

Chips

Nordic RF5 Nordic Semiconductor TI Texas Instruments Silicon Labs Microchip

ISA Intel/AMD X86-64 ARM Cortex A / M MIPS RISC-V

mips_24kc ath79

Freescale:  : Intel > NXP Broadcom Atheros  : Qualcomm Atmel  : 328P : > Microchip Texas Instruments CC26xx

HUE uses QCA9533 ver 2 rev 0, which is an ATH79 processor, which is a MIPS 24kc build by Atheros, bought by Qualcomm KEdge uses an NXP i.MX8 Nano, which is an ARM A7 processor, built by Freescale, bought by NXP

ATSAMR21E18A

https://erik-engheim.medium.com/interesting-random-facts-about-arm-x86-risc-v-and-mips-7e670b249222 https://www.mips.com/products/architectures/mips32-2/ https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html

Micro Processor / Controller (sliding scale) ARM Cortex A7

NXP i.MX8

RISC-V

TI

ARM Cortex M4 STM32

Radio 2.4Ghz Espressif ESP32, S-C-H

=

Arduino Espressif SDK Platform.IO

=== Linux DTD Tree BSP BoardSupport Package CPU Support Yocto

Linux needs depends on Memory Mapper

STM32 MCUBoot NRF91 SBSU Boot

=== RTOS FreeRTOS Mynewt Zephyr

=== IEEE 802 https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=68

IEEE 802(R): Overview and Architecture IEEE 802.1: Bridging and Management IEEE 802.3: Ethernet IEEE 802.11: Wireless LANs IEEE 802.15: Wireless PANs IEEE 802.16: Broadband Wireless MANs IEEE 802.19: TV White Space Coexistence Methods IEEE 802.21: Media Independent Handover Services IEEE 802.22: Wireless Regional Area Networks

802.1X 802.1AR 802.3 Ethernet 802.11 WIFI 802.15.4

=== IEEE 802.15.4 ISM Band, Wifi overlapping channels, Bluetooth 80x1Mhz, BLE 40x2Mhz

Bluetooth Classic Bluetooth BLE Bluetooth Mesh Zigbee ZWave (not 2.4ghz)

=== Zigbee https://zigbeealliance.org/wp-content/uploads/2019/11/docs-05-3474-21-0csg-zigbee-specification.pdf Commisioning LightTouch

=== Thread CSA Zigbee Controller, End-Device https://openthread.io/guides/border-router https://www.threadgroup.org/ThreadSpec https://openthread.io/guides/thread-primer

docker pull openthread/environment:latest docker run --name codelab_otsim_ctnr -it --rm \

  --sysctl net.ipv6.conf.all.disable_ipv6=0 \
  --cap-add=net_admin openthread/environment bash

/openthread/build/examples/apps/cli/ot-cli-ftd 1 dataset init new dataset dataset commit active ifconfig up thread start state ipaddr

docker exec -it codelab_otsim_ctnr bash /openthread/build/examples/apps/cli/ot-cli-ftd 2 dataset networkkey e4344ca17d1dca2a33f064992f31f786 dataset panid 0xc169 dataset commit active thread start state

rloc16 router table

thread stop factoryreset

// on 1 commissioner start commissioner joiner add * J01NME

// on 2 joiner start J01NME

state

mkdir -p /dev/net mknod /dev/net/tun c 10 200 chmod 600 /dev/net/tun

/openthread/build/posix/src/posix/ot-daemon -v 'spinel+hdlc+forkpty:///openthread/build/examples/apps/ncp/ot-rcp?forkpty-arg=2' eui64

commissioner start commissioner joiner add 18b4300000000001 J01NME

ifconfig up joiner start J01NME

thread start state ping6 -c 4 fd55:cf34:dea5:7994:460:872c:e807:c4ab

=== Matter https://github.com/project-chip/connectedhomeip

=== Commisioning, Provisisioning

=== IOT MQTT CoAP OMA LWM2M

=== Cloud Analytics

=== PlatformIO RTL8196E GD25Q127

cd C:\Users\me\.platformio\packages\framework-espidf\components\esptool_py\esptool python.exe .\esptool.py ESP32-D0WDQ6 (revision 1) 4c:11:ae:74:63:b0

python.exe .\esptool.py --port com3 --baud 115200 version python.exe .\esptool.py --port com3 --baud 115200 chip_id python.exe .\esptool.py --port com3 --baud 115200 flash_id --spi-connection HSPI python.exe .\esptool.py --port com3 --baud 115200 read_flash_status --spi-connection HSPI python.exe .\esptool.py --port com3 --baud 115200 read_flash --spi-connection HSPI 0 0x400000 flash_dump.bin python.exe .\esptool.py --port com3 --baud 460800 read_flash --spi-connection SPI 0 0x1600000 flash_16m.bin

python.exe .\esptool.py --port com3 --baud 460800 --no-stub read_flash --spi-connection HSPI 0 16777216 new_16m.bin

python.exe .\esptool.py --port com3 --baud 460800 --no-stub read_flash --spi-connection HSPI 0 0x2000 boot.bin

--flash_mode qio

python.exe .\esptool.py --port com3 --baud 460800 --before default_reset --after hard_reset erase_flash --spi-connection SPI python.exe .\esptool.py --port com3 --baud 460800 --before default_reset --after hard_reset write_flash --spi-connection SPI 0x0 flash_16m.bin

(choose from 'load_ram', 'dump_mem', 'read_mem', 'write_mem', 'write_flash', 'run', 'image_info', 'make_image', 'elf2image', 'read_mac', 'chip_id', 'flash_id', 'read_flash_status', 'write_flash_status', 'read_flash', 'verify_flash', 'erase_flash', 'erase_region', 'merge_bin', 'get_security_info', 'version')

Values are SPI, HSPI, or a sequence of 5 pin numbers CLK,Q,D,HD,CS) SPI0 and SPI1 are the first SPI bus with two chips connected to Flash and RAM SPI is the V-SPI? HSPI is the HSPI?

https://alu.dog/posts/livarno-lux/ https://zigbee.blakadder.com/Lidl_TYGWZ-01.html https://github.com/banksy-git/lidl-gateway-freedom/tree/master/scripts